The functional operation of a digital to analog converter (DAC) is well known. Generally, a DAC accepts an digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. DACs are useful to interface digital systems to analog systems. Applications of DACs include video or graphic display drivers, audio systems, digital signal processing systems, function generators, digital attenuators, precision instruments and data acquisition systems including automated test equipment.
There are a variety of DACs available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the DACs available may have different predetermined resolutions of a digital input signal, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally there are a number of DAC performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide which defines the resolution, the number of output levels or quantization levels and the total number of digital codes that are acceptable. If the digital input signal is m-bits wide, there are 2.sup.m output levels and 2.sup.m-1 steps between levels. The range of analog output signal values usually depend upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference DAC. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying DACs. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a DAC varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof are used to construct DACs. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (PFET) or CMOS technology having both PFETs and NFETs.
Referring now to FIG. 1A, a block diagram of a DAC 100 has a digital input signal DIN 101, a positive analog supply voltage level AVref+104, and a negative analog supply voltage level AVref-105 in order to generate an analog voltage output signal on the DAC output terminal AVOUT 110. Alternatively DAC 100 can generate an analog current output signal with minor changes to its circuit configuration. For simplicity in discussion, consider DAC 100 to be a fixed reference DAC such that the output voltage range of AVOUT 110 is a function of DIN 101 and the range of voltage is defined by the predetermined voltage levels of AVref+104 and AVref-105. DIN 101 is m bit wide. The predetermined value of m is the resolution of the DAC. The selected circuitry for DAC 100 varies depending upon a number of factors including power supply range and desired parameters of input and output signals. As illustrated in FIG. 1B, DAC 100 includes a signal converter 112 coupled to an amplifier or buffer 114. Some forms of DACs, specifically current output DACs, may not include the buffer 114 and require external amplification. Signal converter 112 converts DIN 101 into a form of analog signal on the intermediate signal line VLADR 120 which is input to buffer 114. Buffer 114 buffers the analog signal generated by the signal converter 112 from a load that may be coupled to the DAC output terminal AVOUT 110. The signal converter 112 includes a switched R-2R ladder 116 and a switch controller 118. Switch controller 118 controls switches within the switched R-2R ladder 116 to cause it to convert the value of DIN 101 into an analog signal.
Referring now to FIG. 2A, a prior art switched R-2R ladder 116 is illustrated. The switched R-2R ladder 116 is a 4 bit inverted R-2R ladder to provide an analog voltage output signal but may be easily expanded to m-bits with the addition of other intermediate R-2R switch legs and additional switch control lines. Alternatively, a non-inverted R-2R ladder could be used to provide an analog current output signal. Signals DBn/DBp 201 are selectively controlled by the switch controller 118 in order to generate an analog voltage output signal VLADR 120. DBn/DBp 201 switches ON and OFF NFETS 211-214 and PFETS 216-219 in order to change the voltage division of the R-2R resistor network between AVref+104 and AVref-105 and VLADR 120. Inverters 246-249 generate the inverter polarity of the switch control lines D4Bp-D1Bp 241-244 to control the NFETs 236-239 to form fully complementary switches with PFETs 216-219. NFET 211 and PFET 216/NFET 236 represent the MSB of the DAC and can couple 8/16 of the reference voltage range to VLADR 120. NFET 212 and PFET 217/NFET 237 can couple 4/16 of the reference voltage range to VLADR 120. NFET 213 and PFET 218/NFET 238 can couple 2/16 of the reference voltage range to VLADR 120. NFET 214 and PFET 219/NFET 239 represent the LSB of the DAC and can couple 1/16 of the reference voltage range to VLADR 120. Thus, when the digital code is 1111, PFETs 216-219 and NFETs 236-239 are all ON and NFETS 211-214 are all OFF such that 15/16 of the reference voltage range is coupled to VLADR 120. When the digital code is 0000, NFETS 211-214 are all ON and PFETs 216-219 and NFETs 236-239 are all OFF such that no current flows between AVref+104 and AVref-105 in a resistor and AVref-105 is coupled to VLADR 120.
The circuit connections of the switched R-2R ladder 116 are now described. NFET 215 has its gate tied to terminal leg gate voltage signal, TLGV 235, such that it is constantly turned ON. The voltage level of TLGV 235 is the same as the turn ON voltage level for all the NFETs 211-214 switching AVref-in the switched R-2R ladder 116. NFETS 211-215 have sources connected to AVref-105 and drains respectively connected to first ends of resistors 220-223. PFETS 216-219 have sources connected to AVref+104 and drains respectively connected to first ends of resistors 220-224. NFETs 236-239 have sources respectively connected to the first ends of resistors 220-223 and drains connected to AVref+104. The gates of NFETS 211-214 are respectively connected to signals D4Bn-D1Bn 231-234 and gates of PFETS 216-219 are respectively connected to signals D4Bp-D1Bp 241-244 of DBn/DBp 201. The inverters 246-249 have inputs respectively coupled to signals D4Bp-D1Bp 241-244 to generate the inverted polarity for coupling their outputs to the gates of NFETs 236-239 respectively. Signals D4Bn-D1Bn 231-234 and signals D4Bp-D1Bp 241-244 are collectively referred to as signals DBn/DBp 201 from switch controller 118. Resistors 220-223 each have a resistance value of 2R. Resistors 224-228 each having a resistance value of R are coupled in series together with a first end of resistor 228 coupled to VLADR 120. A second end of resistor 224 is coupled to a second end of resistor 225 at node 250 while a second end of resistor 220 is coupled to VLADR 120. Resistors 223, 225, and 226 each have an end coupled to node 251. Resistors 222, 226, and 227 each have an end coupled to node 252. Resistors 221, 227, and 228 each have an end coupled to node 253. The MSB leg of the switched R-2R ladder 116 is defined as NFET 211/PFET 216/NFET 236 and resistor 220, the LSB leg as NFET 214/PFET 219/NFET 239 and resistors 223 and 226, and the termination leg as NFET 215 and resistors 224-225. The intermediate legs of the switched R-2R ladder 116 are NFET 213/PFET 218/NFET 238 and resistors 222 and 227 and NFET 212/PFET 217/NFET 237 and resistors 221 and 228.
PFETS and NFETS are scaled because of the binary weighting from LSB to MSB. For example, if NFET 214/PFET 219/NFET 239 switches are weighted 1.times., NFET 213/PFET 218/NFET 238 switches are weighted 2.times., NFET 212/PFET 217/NFET 237 switches are weighted 8.times., and NFET 211/PFET 216/NFET 236 switches are weighted 16.times. in transistor size to reduce the RON of the transistors. This reduces user trimming for a drift that would otherwise be introduced by mismatched RON resistances when the transistor switches are turned ON and OFF. NFET 215 is provided in the termination leg to match RON of the MSB switch (NFET 214). Preferably, NFETS 211-215, PFETS 216-219, and NFETs 236-239 operate in their linear region to maintain linearity of the DAC.
As previously discussed, there are a number of DAC performance factors to consider including certain DAC speed factors such as settling time and full scale transition time. Full scale transition time is the time required for a DAC output to swing during a transition from a zero digital input to a full scale digital input from 10% to 90% of the output voltage value or a transition from a full scale digital input to a zero digital input from 90% to 10% of the output voltage value. Settling time is the time required for a DAC output voltage on AVOUT 110 to settle to within the error value, such as one half of the LSB value, of the desired output voltage value during a full scale transition. There is a positive settling time for a full scale transition from zero digital input to a full scale digital input and a negative settling time for a full scale transition from a full scale digital input to a zero digital input.
Other performance factors to consider associated with a digital to analog converter is glitch impulses and their associated glitch amplitude on AVOUT 110. Primary glitch impulses and their associated amplitudes are related to the switching ON and OFF of NFETS 211-214 and PFETS 216-219 of the R-2R ladder 116 in order to change the R-2R resistor network between AVref+104 and AVref-105 and VLADR 120 to generate an analog voltage level on VLADR 120 a function of DIN 101. FIG. 2B is a timing diagram illustrating the glitch impulses and their associated amplitudes. When DIN 101 switches to change state, an idealized DAC would immediately respond by transitioning to the new analog level after some time delay. The idealized AVOUT waveform 110A illustrates the immediate transition to a new analog level. In actuality, glitch impulses 261-262 are generated in prior art DACs which cause additional ringing in AVOUT 110 before settling to the proper analog level.
Primary glitch impulses are ordinarily known to be associated with the major carry transitions of the DAC. This is where the input code changes to cause the MSB to change state as compared with the other order bits of DIN 101. For example, a major carry transition occurs when the leg of the R-2R ladder 116 is caused to turn ON while the lower order bits are turned OFF. However, additional lower amplitude primary glitch impulses occur as a result of the gates of the NFETS and PFETS in the R-2R ladder changing state.
Each of the NFET 211-214 and PFET 216-219 switches have parasitic capacitances associated with them. FIG. 2C illustrates the typical parasitic capacitances associated with a MOSFET such as an NFET or PFET. The gate to source capacitance Cgs, gate to drain capacitance Cgd, and gate to substrate or body capacitance Cgsub contribute most greatly to the glitch impulses and the lower order amplitudes. As the gate of the NFET 211-214 and PFET 216-219 switches of the R-2R ladder 116 change state, the parasitic capacitance of Cgsub, Cgs and Cgd cause charge sharing, also referred to as clock feedthrough, to occur with the capacitance in the R-2R ladder and on VLADR 120. If the NFET/PFET pairs of the NFET 211-214 and PFET 216-219/NFET 236-239 switches could switch simultaneously, gates of the PFET/NFET pairs changing to an opposite state of the NFETS, the charge sharing and would mostly be canceled and any glitch would be relatively small. However, the NFET/PFET pairs of the NFET 211-214 and PFET 216-219 switches can not switch simultaneously because to do so would result in crowbar currents between power supplies. Thus, switch controller 118 provides for break before make timing of switching the NFET 211-214 and PFET 216-219 switches generating a timing slew between NFET switch control signals driving the NFETS and PFET/NFET switch control signals driving the gates of the PFETS/NFETS of the PFET/NFET pairs. Because of the timing slew between NFET switch control signals and PFET/NFET switch control signals, charge cancellation does not occur and charges get coupled to the R-2R ladder and its output VLADR 120. Charges coupled into capacitors and resistors cause voltage spikes. These voltage spikes, referred to as glitch impulses. Charges coupled onto VLADR 120 cause voltage spikes or glitch impulses which are then coupled into the buffer 114 and driven out onto AVOUT 110 as amplified glitch impulses.
The problem of glitch impulses associated with the NFET 211-214 and PFET 216-219/NFET 236-239 switches of the R-2R ladder is exacerbated when it is desirable to design DACs with increased resolution. This is because more PFET and NFET switches in the switched R-2R ladder 116 and more digital lines DBn/DBp 201 are changing state to provide greater resolution. Additionally, the amplitude of glitch impulses is increased when it is desired to provide a higher voltage range between AVref+104 and AVref-105 because of larger voltage swings during the major carry transitions of the DAC.
Prior art methods of controlling the glitch impulses include adding a large capacitor to the output VLADR 120 of R-2R ladder 116. The combination of the resistance in the R-2R ladder 116 and the large capacitor act as a low pass filter reducing the amplitude of the glitches before reaching the input of the buffer 114. However, to significantly reduce the amplitude of the glitches, the capacitor coupled to VLADR 120 must be sufficiently large which causes the settling times of the DAC to significantly increase. Increases in settling time of a DAC are undesirable.
Another prior art method of controlling the glitch impulses, without increasing the transition time and settling time, is to provide a sample and hold circuit at the output AVout 110 of DAC 100 which is disclosed in "Bipolar and MOS Analog Integrated Circuit Design" by Alan B. Grebene 1984 (pages 754 and 770). Referring to FIG. 2D, a sample and hold circuit 270 is illustrated coupled to the output AVOUT 110 of DAC 100. The sample and hold circuit 270 includes a track and hold switch T/H SW 272, a capacitor 274, and a buffer or amplifier 276. It was thought that by sampling the output AVOUT 110 of the DAC 100 after conversion is completed and the glitch impulses 261-262 have settled out, the output of the sample and hold SAHout 277 may be free from glitches. This may be the case with idealized circuitry, however, the track and hold switch T/H SW 272 is usually implemented by using an NFET, PFET or both NFET and PFET switches in parallel which when switched generates parasitic charges.
Referring now to FIG. 2E, a cross section of a MOSFET provided as the T/H SW 272 is illustrated with voltages being applied to its terminals. The voltages applied across the drain to source, gate to source, and gate to substrate terminals cause a channel charge 280 to be induced in the substrate or body 281 of the transistor when the gate is switched ON. This channel charge 280 needs to be dissipated when the gate of the track and hold switched T/H SW 272 is switched OFF. When switched ON, the channel charge 280 needs to be induced. When the gate of the MOSFET changes state to turn OFF T/H SW 272, the channel charge 280 is released from the channel into the MOSFET's source and drain. When the gate changes state to turn the T/H SW 272 ON, the channel charge 280 is supplied from the source and drain into the channel. This phenomenon is referred to as charge injection. Charge injection couples charges into the capacitance of the sample and hold circuit 270, including the capacitor 274, such that rather large voltage spikes or secondary glitch impulses are generated due to the switching of the track and hold switch T/H SW 272. From the parasitic capacitance associated with FIG. 2C, clock feedthrough also occurs when switching of the track and hold switch T/H SW 272. Thus, by simply providing a sample and hold circuit 270 at the output of DAC 100, charges may still be coupled into the sample and hold circuit 270 and cause secondary glitch impulses at the output SAHout 277. Thus, it is desirable to provide additional circuitry around the sample and hold circuit 270 such that charges coupled thereto are reduced and the secondary glitch impulses substantially eliminated. However, even charge cancellation circuitry can introduce low amplitude glitches during sample and hold transitions into the output of a sample and hold circuit 270. It is desirable to additionally provide another means for avoiding such low amplitude glitches.
Usually the track and hold switch T/H SW 272 is controlled by a clock signal that drives the gate of a PFET and/or NFET switch periodically. The periodic switching of the PFET and/or NFET couples charges into the hold capacitor of the sample and hold circuitry introducing glitch impulses of its own. However, it is not always the case that the track and hold switch T/H SW 272 needs to be periodically driven by a clock signal to cycle back and forth between sample and hold periods. For example, if the digital input signal DIN 101 does not change state, there is no transition in the DAC 100 and switches in the switched R-2R ladder 116 are not transitioned between ON and OFF states. Thus, no glitch impulse occurs because there is no change in DIN 101 and the output VLADR 120 of the R-2R ladder 116 is stable. To switch the sample and hold circuit 270 during this condition, unnecessarily injects charges into the sample and hold and produces the secondary glitch impulses. Thus, it is desirable to further control the track and hold switch T/H SW 272 of a sample and hold circuit 270 such that secondary glitch impulses at the output of a DAC 100 are further reduced.